Field
The disclosed embodiments relate to power-management techniques for multi-core processor systems. More specifically, the disclosed embodiments relate to a power-management technique that facilitates high-frequency operation of processor cores in a multi-core processor system.
Related Art
Modern computer systems typically utilize multiple processors and/or processor cores to increase computational performance. Processors in a multiprocessor system may additionally be configured to run at various speeds through a power-management system that feeds different operating voltages and/or frequencies into the processors. For example, a four-core processor system with two idle cores may temporarily overclock the two non-idle cores by allocating power normally used to operate the idle cores to the non-idle cores.
However, the high-frequency execution of non-idle cores in a multi-core processor system may be limited by the subsequent asynchronous execution of the idle cores. For example, a timer queue for an idle core may include an asynchronous wakeup event that causes the core to resume operation some time in the future. If the core resumes operation during high-frequency operation of other cores in the multi-core processor system, the additional power required to resume execution of the core at high frequency may overload the power supply for the multi-core processor system, and in turn, cause the multi-core processor system to fail. To prevent such failure, overclocking of non-idle cores is often avoided when idle cores are associated with impending wakeup events.
A technique disclosed in parent patent application Ser. No. 12/886,431 listed above facilitates high-frequency operation of non-idle cores in conjunction with such asynchronous wakeup events. More specifically, after creation of an asynchronous wakeup event, when a processor core is placed into an idle state, this technique configures the processor core to resume operation at a reduced frequency that is a fraction of an operating frequency for the multi-core processor system. Note that this reduced frequency allows more power to be allocated to other processor cores in the multi-core processor system and makes it easier for processor cores in the system to operate in an overclocked mode. This technique works well, but unfortunately the technique requires the power-management unit in a multi-core processor to be modified, which means that the technique cannot be used with existing multi-core processor chips which are not so modified.
Hence, what is needed is a technique for facilitating high-frequency operation of non-idle cores in conjunction with asynchronous wakeup events, wherein the technique can be used with existing multi-core processors.